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sn74lvc1g386 www.ti.com sces439e ? april 2003 ? revised december 2013 single 3-input positive-xor gate check for samples: sn74lvc1g386 1 features description the sn74lvc1g386 device performs the boolean 2 ? available in the texas instruments function y = a b c in positive logic. nanostar ? and nanofree ? packages nanostar ? and nanofree ? package technology is a major breakthrough in ic packaging concepts, ? supports 5-v v cc operation using the die as the package. ? inputs accept voltages to 5.5 v this device is fully specified for partial-power-down ? supports down translation to v cc applications using i off . the i off circuitry disables the ? i off supports live insertion, partial-power- outputs, preventing damaging current backflow down mode, back-drive protection through the device when it is powered down. ? latch-up performance exceeds 100 ma per jesd 78, class ii ? esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) ? 200-v machine model (a115-a) ? 1000-v charged-device model (c101) 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 nanostar, nanofree are trademarks of texas instruments. production data information is current as of publication date. copyright ? 2003 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. see mechanical drawings for dimensions. dbv package (top view) 2 gnd v cc 5 3 4 b y 6 1 a c dck package (top view) 3 4 b 2 gnd y 5 1 a v cc 6 c dry package (top view) gnd v cc a 6 5 4 2 3 b y c 1 yzp package (bottom view) gnd v cc a b 21 3 y 5 46 c a b dsf package (top view) gnd c y v cc 6 5 4 2 3 1
sn74lvc1g386 sces439e ? april 2003 ? revised december 2013 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. function table inputs output y a b c l l l l l l h h l h l h l h h l h l l h h l h l h h l l h h h h logic diagram (positive logic) absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range ? 0.5 6.5 v v i input voltage range (2) ? 0.5 6.5 v v o voltage range applied to any output in the high-impedance or power-off state (2) ? 0.5 6.5 v v o voltage range applied to any output in the high or low state (2) (3) ? 0.5 v cc + 0.5 v i ik input clamp current v i < 0 ? 50 ma i ok output clamp current v o < 0 ? 50 ma i o continuous output current 50 ma continuous current through v cc or gnd 100 ma dbv package 165 ja package thermal impedance (4) dck package 259 c/w yep or yzp package 123 t stg storage temperature range ? 65 150 c (1) stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) the value of v cc is provided in the recommended operating conditions table. (4) the package thermal impedance is calculated in accordance with jesd 51-7. 2 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: sn74lvc1g386 ac b y
sn74lvc1g386 www.ti.com sces439e ? april 2003 ? revised december 2013 recommended operating conditions (1) min max unit operating 1.65 5.5 v cc supply voltage v data retention only 1.5 v cc = 1.65 v to 1.95 v 0.65 v cc v cc = 2.3 v to 2.7 v 1.7 v ih high-level input voltage v v cc = 3 v to 3.6 v 2 v cc = 4.5 v to 5.5 v 0.7 v cc v cc = 1.65 v to 1.95 v 0.35 v cc v cc = 2.3 v to 2.7 v 0.7 v il low-level input voltage v v cc = 3 v to 3.6 v 0.8 v cc = 4.5 v to 5.5 v 0.3 v cc v i input voltage 0 5.5 v v o output voltage 0 v cc v v cc = 1.65 v ? 4 v cc = 2.3 v ? 8 i oh high-level output current ? 16 ma v cc = 3 v ? 24 v cc = 4.5 v ? 32 v cc = 1.65 v 4 v cc = 2.3 v 8 i ol low-level output current 16 ma v cc = 3 v 24 v cc = 4.5 v 32 v cc = 1.8 v 0.15 v, 2.5 v 0.2 v 20 t/ v input transition rise or fall rate v cc = 3.3 v 0.3 v 10 ns/v v cc = 5 v 0.5 v 5 t a operating free-air temperature ? 40 125 c (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004 . copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: sn74lvc1g386
sn74lvc1g386 sces439e ? april 2003 ? revised december 2013 www.ti.com electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) ? 40 c to 85 c ? 40 c to 125 c parameter test conditions v cc unit min typ (1) max min typ (1) max 1.65 v to i oh = ? 100 a v cc ? 0.1 v cc ? 0.1 5.5 v i oh = ? 4 ma 1.65 v 1.2 1.2 i oh = ? 8 ma 2.3 v 1.9 1.9 v oh v i oh = ? 16 ma 2.4 2.4 3 v i oh = ? 24 ma 2.3 2.3 i oh = ? 32 ma 4.5 v 3.8 3.8 1.65 v to i ol = 100 a 0.1 0.1 5.5 v i ol = 4 ma 1.65 v 0.45 0.45 i ol = 8 ma 2.3 v 0.3 0.3 v ol v i ol = 16 ma 0.4 0.4 3 v i ol = 24 ma 0.55 0.55 i ol = 32 ma 4.5 v 0.55 0.55 i i all inputs v i = 5.5 v or gnd 0 to 5.5 v 5 5 a i off v i or v o = 5.5 v 0 10 10 a 1.65 v to i cc v i = 5.5 v or gnd, i o = 0 10 10 a 5.5 v one input at v cc ? 0.6 v, i cc 3 v to 5.5 v 500 500 a other inputs at v cc or gnd c i v i = v cc or gnd 3.3 v 3.5 pf (1) all typical values are at v cc = 3.3 v, t a = 25 c. 4 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: sn74lvc1g386
sn74lvc1g386 www.ti.com sces439e ? april 2003 ? revised december 2013 switching characteristics over recommended operating free-air temperature range, c l = 15 pf (unless otherwise noted) (see figure 1 ) ? 40 c to 85 c from to v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v parameter unit (input) (output) 0.15 v 0.2 v 0.3 v 0.5 v min max min max min max min max t pd a, b, or c y 3 9.4 1.3 5 0.8 4.5 0.5 3.5 ns switching characteristics over recommended operating free-air temperature range, c l = 30 pf or 50 pf (unless otherwise noted) (see figure 2 ) ? 40 c to 85 c from to v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v parameter unit (input) (output) 0.15 v 0.2 v 0.3 v 0.5 v min max min max min max min max t pd a, b, or c y 3.5 12 1.8 5.5 1.3 5 1 4 ns switching characteristics over recommended operating free-air temperature range, c l = 30 pf or 50 pf (unless otherwise noted) (see figure 2 ) ? 40 c to 125 c from to v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v parameter unit (input) (output) 0.15 v 0.2 v 0.3 v 0.5 v min max min max min max min max t pd a, b, or c y 3.5 14.8 1.8 7.2 1.3 6.4 1 5.1 ns operating characteristics t a = 25 c v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v parameter test conditions unit typ typ typ typ c pd power dissipation capacitance f = 10 mhz 17.5 18 19 22 pf copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: sn74lvc1g386
sn74lvc1g386 sces439e ? april 2003 ? revised december 2013 www.ti.com parameter measurement information figure 1. load circuit and voltage waveforms 6 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: sn74lvc1g386 t h t su from output under test c (see note a) l load circuit s1 v load open gnd r l data input timing input 0 v 0 v 0 v t w input 0 v input output waveform 1 s1 at v (see note b) load output waveform 2 s1 at gnd (see note b) v ol v oh 0 v 0 v outputoutput test s1 output control v m v m v m v m v m 1.8 v 0.15 v 2.5 v 0.2 v 3.3 v 0.3 v 5 v 0.5 v 1 m 1 m 1 m 1 m v cc r l 2 v cc 2 v cc 6 v 2 v cc v load c l 15 pf15 pf 15 pf 15 pf 0.15 v 0.15 v 0.3 v 0.3 v v ? 3 v v i v cc /2 v cc /2 1.5 v v cc /2 v m 2 ns 2 ns 2.5 ns 2.5 ns inputs r l t /t r f v cc v cc v cc t (see notes e and f) pzl v load voltage waveforms enable and disable times low- and high-level enabling voltage waveforms propagation delay times inverting and noninverting outputs notes: a. c includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators have the following characteristics: prr 10 mhz, z = 50 . d. the outputs are measured one at a time, with one transition per measurement. e. because this device has open-drain outputs, t and t are the same as t . f. t is measured at v . g. t is measured at v + h. all parameters and waveforms are not applicable to all devices. l o plz pzl pd pzl m plz ol v . ? voltage waveforms pulse duration voltage waveforms setup and hold times v i v i v i v m v m v /2 load t pzl t plz t phz t pzh v C v oh ? v + v ol ? v m v m v m v m v ol v oh v i v i v oh v ol v m v m v m v m t plh t phl t plh t phl t (see notes e and g) plz v load t /t phz pzh v load
sn74lvc1g386 www.ti.com sces439e ? april 2003 ? revised december 2013 parameter measurement information figure 2. load circuit and voltage waveforms copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: sn74lvc1g386 t h t su from output under test c (see note a) l load circuit s1 v load open gnd r l data input timing input 0 v0 v 0 v t w input 0 v input output waveform 1 s1 at v (see note b) load output waveform 2 s1 at gnd (see note b) v ol v oh 0 v? 0 v outputoutput test s1 t /t plh phl open output control v m v m v m v m v m 1.8 v 0.15 v 2.5 v 0.2 v 3.3 v 0.3 v 5 v 0.5 v 1 k w 500 w 500 w 500 w v cc r l 2 v cc 2 v cc 6 v 2 v cc v load c l 30 pf30 pf 50 pf 50 pf 0.15 v0.15 v 0.3 v0.3 v v d 3 v v i v cc /2 v cc /2 1.5 v v cc /2 v m 2 ns 2 ns 2.5 ns 2.5 ns inputs r l t /t r f v cc v cc v cc v load t /t plz pzl gnd t /t phz pzh voltage waveforms enable and disable times low- and high-level enabling voltage waveforms propagation delay times inverting and noninverting outputs notes: a. c includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z = 50 . d. the outputs are measured one at a time, with one transition per measurement. e. t and t are the same as t . f. t and t are the same as t . g. t and t are the same as t . h. all parameters and waveforms are not applicable to all devices. l o plz phz dis pzl pzh en plh phl pd w voltage waveforms pulse duration voltage waveforms setup and hold times v i v i v i v m v m v /2 load t pzl t plz t phz t pzh v C v oh d v + v ol d v m v m v m v m v ol v oh v i v i v oh v ol v m v m v m v m t plh t phl t plh t phl
sn74lvc1g386 sces439e ? april 2003 ? revised december 2013 www.ti.com revision history changes from revision d (july 2006) to revision e page ? updated document to new ti data sheet format. ................................................................................................................. 1 ? updated features. ................................................................................................................................................................ 1 ? added esd warning. ............................................................................................................................................................ 2 ? updated operating temperature range. ................................................................................................................................. 3 8 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: sn74lvc1g386
package option addendum www.ti.com 18-sep-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 74lvc1g386dckrg4 active sc70 dck 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c8r SN74LVC1G386DBVR active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cc6r sn74lvc1g386dckr active sc70 dck 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c8r sn74lvc1g386dryr active son dry 6 5000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c8 sn74lvc1g386dsfr active son dsf 6 5000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c8 sn74lvc1g386yzpr active dsbga yzp 6 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 (c87 ~ c8n) (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 18-sep-2015 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN74LVC1G386DBVR sot-23 dbv 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g386dckr sc70 dck 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 q3 sn74lvc1g386dryr son dry 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 q1 sn74lvc1g386dsfr son dsf 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 sn74lvc1g386yzpr dsbga yzp 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 q1 package materials information www.ti.com 5-jun-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN74LVC1G386DBVR sot-23 dbv 6 3000 202.0 201.0 28.0 sn74lvc1g386dckr sc70 dck 6 3000 202.0 201.0 28.0 sn74lvc1g386dryr son dry 6 5000 184.0 184.0 19.0 sn74lvc1g386dsfr son dsf 6 5000 184.0 184.0 19.0 sn74lvc1g386yzpr dsbga yzp 6 3000 220.0 220.0 35.0 package materials information www.ti.com 5-jun-2014 pack materials-page 2

www.ti.com c 6x 0.22 0.12 6x 0.45 0.35 2x 0.7 4x 0.35 0.4 max 0.05 0.00 a 1.05 0.95 b 1.05 0.95 (0.11) typ (0.1) pin 1 id 4208186/f 10/2014 pin 1 index area seating plane 0.05 c 1 3 4 6 0.07 c a b 0.05 c symm symm notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. reference jedec registration mo-287, variation x2aaf. mechanical data dsf (s-px2son-n6) plastic small outline no-lead

www.ti.com package outline c 0.5 max 0.19 0.15 1 typ 0.5 typ 6x 0.25 0.21 0.5 typ b e a d 4219524/a 06/2014 dsbga - 0.5 mm max height yzp0006 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. nanofree tm package configuration. nanofree is a trademark of texas instruments. ball a1 corner seating plane ball typ 0.05 c b a 1 2 0.015 c a b symm symm c scale 9.000d: max = e: max = 1.418 mm, min = 0.918 mm, min = 1.358 mm0.858 mm
www.ti.com example board layout 6x ( )0.225 (0.5) typ (0.5) typ ( ) metal 0.225 0.05 max solder mask opening metal under mask ( ) solder mask opening 0.225 0.05 min 4219524/a 06/2014 dsbga - 0.5 mm max height yzp0006 die size ball grid array notes: (continued) 4. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number sbva017 (www.ti.com/lit/sbva017). symm symm land pattern example scale:40x 1 2 a b c non-solder mask defined (preferred) solder mask details not to scale solder mask defined
www.ti.com example stencil design (0.5) typ (0.5) typ 6x ( 0.25) (r ) typ0.05 metal typ 4219524/a 06/2014 dsbga - 0.5 mm max height yzp0006 die size ball grid array notes: (continued) 5. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm solder paste example based on 0.1 mm thick stencil scale:40x 1 2 a b c
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